1. Technical Field
The present invention relates to an address pin reduction mode (APRM) circuit and method to test a semiconductor memory device, and more particularly, to an address pin reduction mode circuit based on parallel input-based addressing including a common pin for address pins and data enable/disable pins.
2. Discussion of Related Art
In general, a semiconductor device is fabricated on a wafer where various circuits are formed. The wafer is then divided into chips. Because chips are inherently weak and may be easily contaminated by external impurities, the chips are packaged. Prior to packaging, each chip must be tested by an internal circuit to check for normal operation. An enable signal is applied to a specific pad in order to put a given chip in a test mode. When it is determined that the chip is normal, the chip is then packaged.
A chip test technique is disclosed in a Korean patent Laid-open Publication No. 10-2004-0083695, which discloses a technique where a semiconductor memory device having a plurality of X addresses and a plurality of Y addresses is tested using a DQ-related (data) signal as some of the plurality of X addresses, so that the number of addresses required for testing is reduced.
Nevertheless, test systems for semiconductor memory devices are still limited in the number of signal channels which can be allocated to each device in a parallel test. As the size of semiconductor memory devices increases, so too does the number of pins on the memory device. The increase in the number of pins is due to address increase in the semiconductor memory device. And for each new pin, the number of memory devices that can be tested in parallel is inevitably reduced by ½. For example, when a semiconductor memory device has 20 pins, the test system can test 64 semiconductor memory devices. Whereas when a semiconductor memory device has 21 pins, the test system can test only 32 semiconductor memory devices. That is, the number of semiconductor memory devices that can be tested at a time is reduced from 64 to 32, e.g., by ½, which as a result, increases test costs. Thus, a variety of mode register set (MRS) modes for shortening a test time and increasing parallel test capacity can be used, such as a merged DQ mode (MDQ), an address pin reduction (APR) mode based on serial addressing, and a parallel bit test mode.
The MDQ mode suffers from a test coverage risk because only a limited number of input/output (I/O) data formats are available for each merged DQ. When a memory device is a multi chip package (MCP) product, the MDQ mode is not available in a package test process when other chips are in the MDQ mode and input/output (I/O) is unavailable. In addition, the MDQ mode does not guarantee an optimal user environment because of inconsistently set data pins.
The conventional address pin reduction (APR) mode implements address pin reduction based on serial addressing in which a parallel address is sent in serial. However, serial addressing increases address latch time, such that the intended cost reduction is thwarted.
The parallel bit test mode tests more bits simultaneously in order to shorten the test time and reduce the number of address pins. However, a test coverage issue arises as noise is generated due to simultaneous access to four or eight cells and the number of available input/output (I/O) data formats is reduced. Furthermore, the parallel bit access does not guarantee an optimal user environment based on single bit access.
Accordingly, a need remains for an improved address pin reduction mode circuit and method based on parallel input-based addressing to test a semiconductor memory device.